To keep pace with the demand for ever faster signaling rates, integrated circuit (IC) packaging has evolved from relatively band-limited technologies such as wire-bonded packages to the prior-art flip-chip package 100 illustrated in FIG. 1. The flip-chip package 100 includes an integrated circuit die 103 mounted pad-side down on a multi-layer substrate 105 and enclosed within a non-conductive housing 101. Signal routing structures 110 are disposed within the multi-layer substrate 105 to redistribute signals from the relatively dense arrangement of die pads 107 to a more dispersed ball grid array (BGA) 109 on the underside of the package. The individual contact balls of the BGA 109 may then be soldered to counterpart landings on a printed circuit board.
While generally providing better performance than wire-bonded packages, the flip-chip package 100 presents a number challenges to system designers as signaling rates progress deeper into the gigahertz range. For example, the number of layers needed in substrate 105 for signal redistribution has steadily increased in response to increased numbers of die pads 107, making the flip-chip package 100 more complex and costly. Also, through-hole vias 110 (i.e., vias that extend all the way through the multi-layer substrate) are often used to route signals through the substrate. Unfortunately, unused portions of the vias (e.g., region 112) constitute stubs that add parasitic capacitance and produce signal reflections, both of which degrade signal quality. Although back-drilling and other techniques may be used to reduce the stub portions of the vias, such efforts further increase manufacturing costs and may not be suitable or possible for some package substrate constructions.
Another challenge presented by signal redistribution within the multi-layer substrate 105 is that differences in routing distances tend to introduce timing skew between simultaneously transmitted signals. That is, signals output simultaneously from the die 103 arrive at the BGA contacts 109 at different times, reducing the collective data-valid interval of the signals. In many systems, a single control signal, such as a clock or strobe, is used within a signal receiving device to trigger sampling of multiple simultaneously transmitted signals. Consequently, compression of the collective data-valid interval due to signal skew ultimately limits the maximum signaling rate that can be achieved in such systems without violating receiver setup or hold-time constraints. To avoid such skew-related problems, intricate routing schemes are often employed within the multi-layer substrate 105 to equalize the die-to-contact path lengths, further increasing the complexity and cost of the integrated circuit package 100.
FIG. 2 illustrates a prior art signaling system 120 that includes two flip-chip packages 100A and 100B coupled to one another via signal routing structures disposed within a multi-layer printed circuit board (PCB) 121. From a high-speed signaling perspective, many of the problems resulting from signal redistribution in the integrated circuit packages 100 also result from the multi-layer signal routing within the PCB 121. For example, through-hole vias 123 are often used to conduct signals between PCB layers, presenting stub capacitance and signal reflection problems. Also, the lengths of the signal paths routed between the integrated circuit packages 100A and 100B tend to be different due to different PCB ingress and egress points and different PCB submergence depths of the various traces 126, thereby introducing timing skew. As with the integrated circuit packages 100 themselves, a number of techniques may be used to reduce via stubs, and routing strategies may be used to equalize path lengths, but these solutions tend to increase system complexity and cost.